NPI Product Development DFT Engineer – Noida, Uttar Pradesh – NXP Semiconductors

Job Description


Job title: NPI Product Development DFT Engineer

Company: NXP Semiconductors

Job description: NPI Product Development DFT Engineer

Business Line Description

This vacancy is in the MCU/MPU R&D organization, within the design and quality group responsible for end-to-end Quality for SoCs in the Automotive Processors and/or Advanced microcontrollers in NXP. We ensure Customer and execution quality starting from product introduction and definition, through the NPI SoC development and successful launch and throughout the product lifetime.

Job Summary

  • As a Product Development (DFT) engineer in the team, you will work closely with R&D DFT team, Test and Quality teams to identify innovative DFT techniques needed to achieve and maintain PPB Quality levels.
  • Involves many aspects of Test and DFT in the R&D NPI Design Quality group
  • Collaborate with global cross functional teams to ensure our new leading edge chips meet the Quality standards required for future Autonomous EVs and MCUs and MPUs
  • Support our existing Automotive products and work closely with cross functional teams across NXP to solve customer issues and build the Zero Defect mindset
  • The existing team is a mix of design, product and test, and quality engineers who are experts in their respective functional areas, coming together to solve complex design and to support our customers
  • Great opportunity for someone who is innovative, persistent and curious. You’ll interface with multiple functional areas within R&D as well as the Business, Operations, FA, and Quality teams which will give the right person a real ability to grow their skills and a develop an in depth understanding of the semiconductor industry from R&D to our end Customers.

Key Challenges

  • Ability to work in a global project organization with project team distributed internationally
  • 5+ years in Test and/or Product engineering
  • 5+ years in DFT Methodology/Implementation focusing on SCAN ATPG
  • 5+ years total Industry (SoC) Experience
  • Scan ATPG pattern generation
  • Low-coverage ATPG debug experience is a plus
  • At-speed Scan Diagnostics for Failure Analysis
  • Transition & Path delay testing
  • Memory BIST Algorithm development and implementation
  • JTAG Boundary Scan Design & implementation
  • IC Parametric test methods and implementation
  • Low pin-count test methods
  • Experience with industry standard DFT tools such as Synopsys or Mentor
  • Experience working closely with post-silicon teams (test engineering and failure analysis) is a plus
  • Excellent written and verbal communication skills in English
  • Ability to travel domestically and internationally as needed (~15%)
  • Proven track record in SoC DFT methodology development
  • Direct experience in DFT methods and implementation required
  • Excellent debug skills required

Job Qualifications

  • BSEE / MSEE plus 5-8 years of experience in Physical Design

Job location

  • Bangalore, IN
  • Noida, IN
  • Austin, TX

Expected salary:

Location: Noida, Uttar Pradesh

Job date: Wed, 09 Nov 2022 08:34:01 GMT

Location